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Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
FEATURES
* Metastable immune characteristics * Pin compatible with 74F74 and 74F5074 * Typical fMAX = 200MHz * Output skew guaranteed less than 2.0ns * High source current (IOH = 15mA) ideal for clock driver
applications
PIN CONFIGURATION
RD0 D0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1
* Output capability: +20mA/-15mA * Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
SA00001
PIN DESCRIPTION
PIN NUMBER 2, 12 3, 11 4, 10 1, 13 5, 9 6, 8 7 14 SYMBOL D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Q0, Q1 Q0, Q1 GND VCC NAME AND FUNCTION Data inputs Clock inputs (active rising edge) Set inputs (active-Low) Reset inputs (active-Low) Data outputs (active-Low), non-inverting Data outputs (active-Low), inverting Ground (0V) Positive supply voltage
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs. Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. Data must be stable just one setup time prior to the low-to-high transition of the clock for guaranteed propagation delays. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. The 74ABT5074 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are: 94ps and To 1.3 x 107 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN ICC PARAMETER Propagation delay CPn to Qn or Qn Input capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 2.8 2.4 3 2 UNIT ns pF A
ORDERING INFORMATION
PACKAGES 14-pin plastic DIP 14-pin plastic SOL 14-pin plastic shrink small outline SSOP Type II 14-pin plastic thin shrink small outline (TSSOP) Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C ORDER CODE 74ABT5074N 74ABT5074D 74ABT5074DB 74ABT5074PW DRAWING NUMBER SOT27-1 SOT108-1 SOT337-1 SOT402-1
December 15, 1994
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853-1775 14470
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
LOGIC SYMBOL
2 12
IEC/IEEE SYMBOL
4 D0 D1 3 4 1 11 10 13 CP0 SD0 1 RD0 CP1 10 SD1 RD1 Q0 Q0 Q1 Q1 11 C2 12 2D 13 R 5 6 9 8 8 S 9 R S 3 C1 2 1D 6 5
VCC = Pin 14 GND = Pin 7
SA00002
SA00003
LOGIC DIAGRAM FUNCTION TABLE
INPUTS
SD 4, 10
OUTPUTS D X X X h l X Q H L L H L NC Q L H H L H NC
OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Load "1" Load "0" Hold
SD
1, 13 5, 9 Q
RD H L L H H H
CP X X X
L H L
Q
RD
CP
3, 11
6, 8
H H
D
2, 12
H
VCC = Pin 14 GND = Pin 7
SF00048
NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level
December 15, 1994
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term `metastable immune' to describe characteristics of some of the products in its family. By running two independent signal generators (see Figure 1) at nearly the same frequency (in this case 10MHz clock and 10.02MHz data) the device-under-test can often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur.
After determining the T0 and of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74ABT5074 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74ABT5074 7 nanoseconds after the clock edge. He simply plugs his number into the following equation: MTBF = e(t'/)/ TO*fC*fI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' > h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Figure 2 it is clear that the MTBF is greater than 1010 seconds. Using the above formula the actual MTBF is 1.69 x 1010 seconds or about 535 years.
SIGNAL GENERATOR
D
Q
TRIGGER DIGITAL SCOPE
SIGNAL GENERATOR
CP
Q
INPUT
SA00004
Figure 1. Test Setup
E13
E6
E8
E10
E12
E14
E15 = fc*fi
E12
10,000 YEARS
E11
E10
MTBF (SECONDS)
100 YEARS
E9
E8
ONE YEAR
E7
E6
ONE WEEK
E5 4 5 6 t' (NANOSECONDS) 7 8
VCC = 5V, Tamb = 25C, =94ps, To = 1.3x107 sec
MTBF = e(t'/)/TO*fC*fI
SA00005
Figure 2. Mean Time Between Failures (MTBF) versus t'
December 15, 1994
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
TYPICAL VALUES FOR AND T0 AT VARIOUS VCCS AND TEMPERATURES
VCC 5.5V 5.0V 4.5V Tamb = -40C 84ps 84ps 89ps T0 1.0 x 106 sec 2.7 x 108 sec 93ps 94ps 103ps Tamb = 25C T0 3.8 x 106 sec 1.3 x 107 sec 89ps 106ps 115ps
74ABT5074
Tamb = 85C T0 1.5 x 109 sec 2.2 x 106 sec 4.4 x 106 sec
1.0 x 109 sec
2.1 x 107 sec
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state VI < 0 PARAMETER CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 40 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER MIN 4.5 0 2.0 0.8 -15 20 10 +85 MAX 5.5 VCC V V V V mA mA ns/V C UNIT
December 15, 1994
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH VOL II IOFF IO ICC ICC Input clamp voltage High-level output voltage Low-level output voltage Input leakage current Power-off leakage current Output current1 VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -15mA; VI = VIL or VIH VCC = 4.5V; IOL = 20mA; VI = VIL or VIH VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI v 4.5V VCC = 5.5V; VO = 2.5V VCC = 5.5V; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 Tamb = +25C TYP -0.9 2.9 0.35 0.01 5.0 -75 2 0.25 0.5 1.0 100 -180 50 500 -50 MAX -1.2 2.5 0.5 1.0 100 -180 50 500 Tamb = -40C to +85C MIN MAX -1.2 V V V A A mA A A UNIT
Quiescent supply current Additional supply current per input pin2
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fmax tPLH tPHL tPLH tPHL tsk(o) Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn, RDn to Qn or Qn Output skew1, 2 CPn to Qn to Qn 1 1 2 4 180 1.0 1.0 1.0 1.0 Tamb = +25C VCC = +5.0V TYP 250 2.8 2.4 3.5 3.1 3.9 3.5 4.6 4.2 1.5 MAX Tamb = -40 to +85C VCC = +5.0V 0.5V MIN 150 1.0 1.0 1.0 1.0 4.5 3.7 5.5 4.7 2.0 MAX ns ns ns ns UNIT
NOTES: 1. | tPN actual - tPM actual | for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25C VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) tw (H) tw (L) tw (L) trec Setup time, High or Low Dn to CPn Hold time, High or Low Dn to CPn CPn pulse width, high or low SDn or RDn pulse width, low Recovery time SDn or RDn to CPn 1 1 1 2 3 2.5 2.5 0 0 1.5 2.4 2.0 2.4 TYP 1.5 1.5 -1.4 -1.4 0.6 1.8 1.3 1.3 Tamb = -40 to +85C VCC = +5.0V 0.5V MIN 2.5 2.5 0 0 1.5 2.9 2.2 2.8 ns ns ns ns ns UNIT
December 15, 1994
5
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V The shaded areas indicate when the input is permitted to change for the predictable output performance.
Dn
VM
VM
ts(L)
th(L)
CPn
VM
Qn
Qn
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Time, and Clock Width
SDn or RDn
CPn
Waveform 3. Recovery Time for Set or Reset to Output
December 15, 1994
EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E
VM VM fMAX ts(H) th(H) tw(H) VM tw(L) VM tPLH VM tPHL VM tPHL VM tPLH VM VM tREC VM
EEE EEE EEE EEE
SDn
VM tw(L)
VM
tw(L) RDn tPLH Qn VM VM tPHL VM VM
tPLH Qn tPHL VM VM
SA00008
SA00009
Waveform 2. Propagation Delay for Set and Reset to Output, Set and Reset Pulse Width
Qn, Qn
VM
tSK(0)
Qn, Qn
VM
SA00010
SA00011
Waveform 4. Output Skew
6
Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop with metastable immune characteristics
74ABT5074
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS FAMILY amplitude 74F 3.0V rep. rate 1MHz tw 500ns tR 2.5ns tF 2.5ns
SA00058
December 15, 1994
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